Methods and apparatus for constructing low-density parity check (LDPC) matrix

ABSTRACT

Methods and apparatus for constructing a parity check matrix for use in a low-density parity check (LDPC) coding scheme are provided. The apparatus includes at least one index generator for generating row indexes of “1”s, which indicate row positions of the “1”s in each column of the parity check matrix, wherein the index generator is implemented by a modular shift register generator that generates a row index of a “1” at each clock.

CROSS-REFERENCE TO RELATED PATENT APPLICATIONS

This application claims all benefits of Korean Patent Application No.2004-61797, filed on Aug. 5, 2004, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein in its entiretyby reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to methods and apparatus for constructinga parity check matrix, and more particularly, to methods and apparatusfor constructing a low-density parity check (LDPC) matrix, which canconsiderably reduce memory capacity of encoders and decoders in alow-density parity check (LDPC) coding scheme.

2. Related Art

Recently, various types of coding schemes have been proposed forcommunication and storage systems. One class of codes, generallyreferred to as low-density parity check (LDPC) codes, has been describedas having good error detection and correction performance. In addition,LDPC codes can also be decoded at very high rates of speed. However,such LDPC codes are constructed by random choice of low-density paritycheck (LDPC) matrices, which require complex encoders and decoders witha large amount of memory.

For example, FIG. 1 shows matrices for explaining a concept oflow-density parity check (LDPC) coding and decoding scheme. As shown inFIG. 1, the low-density parity check (LDPC) coding method generatesparity information by using a low-density parity check matrix (H) whoseelements are mostly 0's along with some “1”s.

In the parity check matrix (H), the number of “1”s in each row or columnis referred to as row degree or column degree, respectively. Generally,a parity check matrix whose columns all have the same column degree andwhose rows all have the same row degree is called a regular parity checkmatrix. A parity check matrix whose rows and columns do not all have thesame row degree and column degree is called an irregular parity checkmatrix. In a regular parity check matrix, the row degree is referred toas row weight, Wr, and the column degree is referred to as columnweight, Wc.

Parity information is generated on the basis of a low-density paritycheck (LDPC) coding scheme using the following Equation:HX=0  (1).

In Equation (1), H is an m×n parity check matrix, and X is an n×1codeword matrix. X is comprised of m message information and p parityinformation, so that m+p=n.

A basic concept of LDPC coding is disclosed by D. J. MacKay, “GoodError-correction Codes Based on Very Sparse Matrices”, IEEE Trans. onInformation Theory, vol. 45, no. 2, pp. 399-431, 1999. D. J. Mackaydiscloses that parity information is generated by solving Equation (1)with a matrix algebra, such as a Gaussian Elimination method.

Parity check decoding also includes a procedure for performing a paritycheck on the basis of Equation (1).

There are basically two different techniques of constructing aconventional parity check matrix of LDPC codes. In the first technique,row indexes, which indicate row positions of each “1” in each column ofthe parity check matrix H, are arbitrarily set by a user. For example,row indexes of 1, 3, and 5 may be set for the first column, row indexesof 2, 4, and 6 may be set for the second column, 7, 9, and 11 may be setfor the third column, and so forth. This technique can be easilyimplemented, but has poor bit error rate (BER) performance. In thesecond technique, row indexes, which indicate row positions of “1” ineach column of the parity check matrix H, are determined randomly.Implementation of the second technique is more complicated since rowpositions (indexes) of “1”s are randomly distributed. However, thesecond technique of constructing parity check matrix of LDPC codes hasexcellent BER performance.

An example of the second technique of constructing the parity checkmatrix will now be described as follows.

First, Wc row indexes of element “1”s in the first column aredetermined. Next, arbitrary row indexes of “1”s in the second column aredetermined such that none is the same as row indexes of “1”s in thefirst column. Then, arbitrary row indexes of “1”s for the third columnare determined such that none is the same as row indexes of “1”s in thefirst and second columns. This procedure is repeated through to the lastcolumn.

In summary, in the second technique of constructing a parity checkmatrix, row indexes of “1”s in each column of the parity check matrix Hare set arbitrarily as long as no two columns have the same row index.

According to the second technique of constructing the parity checkmatrix, previously determined row indexes of “1”s should be stored in amemory of an apparatus for constructing the parity check matrix. Also,for encoding or decoding purposes, all the row indexes of “1”s should bestored in a memory of an encoder or a decoder.

FIG. 2 shows a memory structure for storing a parity check matrix. Asshown in FIG. 2, the memory can be a random-access memory (ROM) 20. Theparity check matrix can be defined by row indexes of “1”s, whichrepresent positions of “1”s in each column, and column indexes of “1”s,which represent positions of “1”s in each row. A parity check matrix Hwhich is defined by row indexes of “1”s is stored in the memory 20 forencoding and decoding purposes.

As also shown in FIG. 2, one row index of “1” occupies one address ofthe memory 20. Consequently, the space occupied by one parity checkmatrix is n×Wc×B. Here, B is the number of bits of a row index of the“1”, and 2^(B)=m, where m is the number of rows of the parity checkmatrix.

An example of an m×n parity check matrix having satisfactory BER errorcorrection performance is a 512×(512×17) parity check matrix. The memoryspace required to store the m×n parity check matrix is512(=29)×(512×7)×9 bits. Generally, achieving better BER performancerequires using large amounts of memory to store the parity check matrix.However, using large amounts of memory causes several problems, such as,for example, a substantial increase in the cost of producingcorresponding encoders and decoders.

SUMMARY OF THE INVENTION

An aspect of present invention advantageously provides methods andapparatus for constructing a parity check matrix by using shiftregisters, which can significantly reduce large amounts of memoryrequired for low-density parity check (LDPC) coding and decodingpurposes.

According to an aspect of the present invention, an apparatus isprovided for constructing a low density parity check (LDPC) matrix ofrows and columns, comprising: at least one index generator forgenerating row indexes of “1”s, which indicate row positions of the “1”sin each column of the parity check matrix, wherein the index generatoris implemented by a modular shift register generator (MSRG) thatgenerates a row index of a “1” at each clock.

According to an aspect of the present invention, the index generatorcomprises: s number of registers connected in series which receive aninitial value of s bits, store the initial value bit-by-bit, and eachshift corresponding stored bit to a next register at a clock; a feedbackline through which a bit value stored in a last one of the s registersis selectively fed-back; and an adder connected between every tworegisters, which adds a bit value of a preceding register with thefed-back value and provides the resulting value to a succeedingregister.

According to an aspect of the present invention, the row index is avector of t bits output from “t” number of registers selected from amongthe “s” number of registers, the s and t satisfying the followingequations:m=2^(t)n≦2^(s)−1,

where m is the number of rows and n is the number of columns of theparity check matrix.

According to an aspect of the present invention, the feedback lineincludes a switch with a coefficient chosen such that all the vectorsoutput from the “s” registers during 2^(s)−1 clocks are different fromeach other.

According to an aspect of the present invention, the coefficient of theswitch is chosen from among coefficients of a primitive polynomial p(x)into which x^(v)−1 can be divided, where v is a smallest possiblepositive number satisfying the following equation:

v=p^(u)−1, and where the primitive polynomial is an irreduciblepolynomial of degree of u, having coefficients being any of 0 throughp−1, that is p(x) IN GF(p)[x], the p being any prime number.

According to another aspect of the present invention, a method ofconstructing a low-density parity check (LDPC) matrix comprises:generating at least one index of a “1”, which represents a position ofthe “1” in each column of a parity check matrix, wherein the generationof at least one index is implemented by a modular shift registergenerator (MSRG) that generates a row index of the “1” at each clock.

According to an aspect of the present invention, at least one index isgenerated by: receiving and storing in a register an initial value of“s” bits; selectively feeding back a least significant bit of theinitial value; adding the fed-back bit value to each bit of the initialvalue; and storing as an output vector each of “t: bits selected fromamong the “s” bits resulting from the addition, and outputting the t-bitoutput vector as a row index of the “1”.

According to an aspect of the present invention, the row index of the“1” is a vector of “t” bits output from “t” number of registersarbitrarily selected from among the “s” number of registers, the “s” and“t” satisfying the following equation:m=2^(t)n≦2^(s)−1,

where “m” is the number of rows, and “n” is the number of columns of theparity check matrix.

According to an aspect of the present invention, the selectively feedingback is determined by coefficients of a characteristic polynomial of themodular shift register generator (MSRG), in which the coefficients arechosen such that all vectors output during 2^(s)−1 clocks are different.

According to an aspect of the present invention, the coefficients arechosen from coefficients of a primitive polynomial p(x) into whichx^(v)−1 can be divided, where “v” is a smallest possible positive numbersatisfying the following equation:

v=p^(u)−1, and where the primitive polynomial is a irreduciblepolynomial of degree “u”, having coefficients being any of 0 throughp−1, that is p(x) IN GF(p)[x], the “p” being any prime number.

According to a still another aspect of the present invention, anapparatus for constructing a parity check matrix is provided with: amodular shift register generator which generates indexes of “1”sindicating positions of “1”s in the parity check matrix.

According to an aspect of the present invention, a feedback line of themodular shift register generator (MSRG) is specified by a primitivepolynomial.

According to an aspect of the present invention, an initial value of themodular shift register generator (MSRG) is chosen such that at eachclock none of generated row indexes in a column are the same.

According to a yet another aspect of the present invention, acomputer-readable medium comprising instructions that, when executed bya computer system, act as a modular shift register generator (MSRG) togenerate at least one index of a “1”, which represents a position of the“1” in each column of a parity check matrix at each clock. Such an indexis generated by instructions that include: receiving and storing in aregister an initial value of s bits; selectively feeding back a leastsignificant bit of the initial value; adding the fed-back bit value toeach bit of the initial value; and storing as an output vector each of tbits selected from among the s bits resulting from the addition, andoutputting the t-bit output vector as a row index of the “1”.

Additional aspects and/or advantages of the invention will be set forthin part in the description which follows and, in part, will be obviousfrom the description, or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention will become apparentfrom the following detailed description of example embodiments and theclaims when read in connection with the accompanying drawings, allforming a part of the disclosure of this invention. While the followingwritten and illustrated disclosure focuses on disclosing exampleembodiments of the invention, it should be clearly understood that thesame is by way of illustration and example only and that the inventionis not limited thereto. The spirit and scope of the present inventionare limited only by the terms of the appended claims. The followingrepresents brief descriptions of the drawings, wherein:

FIG. 1 shows matrices for explaining a concept of low-density paritycheck (LDPC) coding and decoding scheme useful in gaining a morethorough appreciation of the present invention;

FIG. 2 shows a memory structure for storing a parity check matrix;

FIG. 3 is a block diagram of an apparatus for constructing a paritycheck matrix according to an embodiment of the present invention;

FIG. 4 is a detailed block diagram of an index generator shown in FIG.3;

FIG. 5 is a block diagram of a first index generator according to anembodiment of the present invention;

FIG. 6 is a table of information regarding the first index generatorshown in FIG. 5;

FIG. 7 is a block diagram of a second index generator according to anembodiment of the present invention;

FIG. 8 is a table of information regarding the second index generatorshown in FIG. 7; and

FIG. 9 is a flowchart of a method of constructing a parity check matrixaccording to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention advantageously provide new efficient methods andapparatus for constructing a low-density parity check (LDPC) matrix foruse in LDPC coding and decoding schemes, which can reduce significantamounts of memory required. Example embodiments of the present inventionwill now be described in detail with reference to the attached drawings.

FIG. 3 is a block diagram illustrating an apparatus 300 for constructinga parity check matrix according to an embodiment of the presentinvention.

Referring to FIG. 3, the apparatus 300 includes a first index generator310, a second index generator 320, . . . , and a Wc-th index generator330. Here, Wc represents a column weight.

The first index generator 310 receives a first initial value 312 of “s”bits, and generates a row index 314 of the first “1” in “t” bits foreach column of the parity check matrix. In more detail, the first indexgenerator 310 outputs a row index (in t bits) of the first “1” for thefirst column at a first clock, generates a row index of the first “1”for the second column at a second clock, generates a row index of thefirst “1” for the third column at a third clock, and so on through tothe last column.

The second through Wc-th index generators 320 through 330 functionanalogously to the first index generator 310.

For example, the second index generator 320 receives an s-bit secondinitial value 322, and generates t bits of a row index 324 of the second“1” for each column of the parity check matrix. That is, the secondindex generator 320 outputs a row index (in t bits) of the second “1”for the first column at the first clock, generates a row index of thesecond “1” for the second column at the second clock, generates a rowindex of the second “1” for the third column at the third clock, and soon through to the last column.

The Wc-th index generator 330 receives an s-bit Wc-th initial value 332,and generates t bits of a row index 334 of the Wc-th “1” for each columnof the parity check matrix. That is, the Wc-th index generator 330outputs a row index (in t bits) of the Wc-th “1” for the first column atthe first clock, generates a row index of the Wc-th “1” for the secondcolumn at the second clock, generates a row index of the Wc-th “1” forthe third column at the third clock, and so on through to the lastcolumn.

Consequently, Wc row indexes indicating positions of “1”s in the firstcolumn are output at the first clock, Wc row indexes indicatingpositions of “1”s in the second column are output at the second clock,Wc row indexes indicating positions of “1” in the third column areoutput at the third clock, and so on through to the last column.

In the apparatus 300 for constructing a parity check matrix, instead ofthe memory shown in FIG. 2 which stores the parity check matrix H ofEquation (1), an encoder or decoder provides the parity check matrix H.

The first initial value 312, the second initial value 322, . . . , andthe Wc-th initial value 332 are each input to the first through Wc-thindex generators 310, 320, and 330, respectively. The initial values aredetermined by a user such that identical values among the first throughthe Wc-th row indexes 314 to 334 are not generated at the same clock.

FIG. 4 is a detailed block diagram of an index generator used in theapparatus 300 shown in FIG. 3.

Since the first through Wc-th index generators 310 through 330 of theapparatus 300 all have the same configuration, and the only differencesare their different coefficients C1, C2, . . . Cs−1 and differentinitial values 312 through 332, each of the index generators 310 through330 can be considered equivalent to an index generator 400 shown in FIG.4, with an initial value 410 and a row index 420.

The index generator 400 includes s number of registers R1, R2, . . . ,Rs, s−1 number of switches 431, 432, . . . , 434, and s−1 number ofadders 401, 402, . . . , 404. The combination of the registers, theadders and the switches is referred to as a modular shift registergenerator (MSRG).

At the first clock, the initial value 410 is input to registers R1, R2,. . . , Rs. A row index 420 corresponds to a value stored in registersR1, R2, . . . , R_(t) at each clock. At the first clock, the initialvalue stored in registers R1, R2, . . . , R_(t) is output as is. The tnumber of registers R1, R2, . . . , R_(t) that output the row index isarbitrarily chosen from among the registers R1, R2, Rs.

Outputs of the registers R1, R2, . . . , Rt correspond to row indexes ofthe “1”s of the parity check matrix H. For example, if t=3, s=4, theinitial value 410 is “1101b”, and registers for outputting the row index420 are chosen to be R1, R2, and R3, the row index 420 can be “110” inbinary, i.e., “6” in decimal, at the first clock. Thus, the row index ofthe first “1” for the first column of the parity check matrix is “6”, sothe 7th element of the first column of the parity check matrix becomes“1” (if the row index of the first “1” is “000b” (“1” in decimal), thefirst element of the first column becomes “1”, if the row index is “001b” (“2” in decimal), the second row of the first column becomes “1”, ifthe row index is “010b” (“3” in decimal), the third row of the firstcolumn becomes “1”, and so forth).

At the second clock, values 421, 422, . . . , and 424 stored inregisters, R1, R2 . . . Rs, are added to outputs 411, 412, . . . , 414of switches 431, 432, . . . , 434, by adders 401, 402, . . . , 404, andthe results are stored respectively in registers, R1, R2 . . . or Rs,next to the adders 401, 402, 403 or 404. Here, each value is “0b”, or“1b”. The outputs 411, 412, . . . , 414 result from switching an outputof the final register Rs fed back through a feedback line 440 atswitches 431, 432, . . . 434, respectively. Coefficients C1, C2, . . . ,Cs−1 are values that indicate whether to switch the fed-back output,each of which is “0” or “1”. At the second clock, values newly stored inregisters, R1, R2 . . . Rs, are output as a second row index 420.

The above procedure is repeated until the n-th clock, and a row index oft bits is output at each clock.

The number “m” of rows and the number “n” of columns of the parity checkmatrix, the number “s” of registers, and the number “t” of registers foroutputting the row index are related by the following Equation:m=2^(t)n≦2^(s)−1  (2)

As shown in the above Equations (2), the number m of rows of the paritycheck matrix is equal to the range 2^(t) of possible indexes of “1”s,and the number n of columns of the parity check matrix is equal to orless than the minimum number of clocks 2^(s)−1.

Coefficients C1, C2, . . . , Cs−1 can be represented by a characteristicequation, such as the following Equation:f(x)=x ^(s) +C _(s−1) x ^(s−1) +C _(s−2) x ^(s−2)+ . . . +C₁ x+C ₀  (3)

The above Equation (3) is the characteristic equation for the indexgenerator 400, where Co=1, and Ci=0 or 1. The characteristic equationspecifies a coupling structure of the feedback line 440 of the modularshift register generator (MSRG).

In an example embodiment of the present invention, the characteristicequation for the index generator 400 is a primitive polynomial withcoefficients C1, C2, . . . , Cs−1 of uniform degree.

The primitive polynomial is an irreducible polynomial p(x) of degree u,into which x^(v)−1 can be divided, where v is a smallest possiblepositive number satisfying the following Equation:v=p ^(u)−1  (4)

Here, in the above Equation (4), the polynomial p(x) is an irreduciblepolynomial with coefficients ranging from 0 to p−1, namely, p(x) inGF(p)[x], where p is any prime number. (An irreducible polynomial is apolynomial that cannot be factorized.)

If the characteristic equation of degree “s”, which indicates thecoupling structure of the feedback line 440 of the index generator 400,is the primitive polynomial, that is, if the coefficients C1, C2, . . ., Cx−1 are chosen to be coefficients of the primitive polynomial,vectors 420 output from s registers R1, R2, . . . , Rs are all differentduring 2^(s)−1 clocks. In other words, each of the vectors that can berepresented by “s” registers is output once.

A more detailed description of the primitive polynomial for use in aMSRG structure is disclosed in “Shift Register Sequence, Holden-Day, SanFrancisco, 1967” by S. W. Golomb, and, as a result, needs not bedescribed herein.

As shown in FIG. 4, if outputs from “t” of “s” registers are chosen tobe the output vector 420, all possible vector values are output with asimilar frequency. In particular, in the case of n=2^(s)−1, all vectorsexcept a zero vector are output as many as 2^(s)−1 times. The zerovector is output 2^(s−1)−1 times.

Therefore, the parity check matrix H constructed by the index generator400 as shown in FIG. 4, has almost-regular low-density parity check(LDPC) codes. Generally, the decoding performance, namely the BERperformance, becomes lower as the maximum row degree becomes larger.However, in the example embodiment of the present invention, asdescribed above, since the probability that “1” appears in each positionof the parity check matrix is almost regular, the decoding performancecan be improved significantly.

Meanwhile, the initial value 410 should be chosen such that differentindex generators do not output the same vector 420 at the same clock.Otherwise, if different index generators generate the same output at thesame clock, positions of “1”s in a column are redundant, resulting in anirregular parity check matrix. The initial value 410 can be determinedthrough a simulation.

FIG. 5 is a block diagram of the first index generator 310 shown in FIG.3, according to an embodiment of the present invention.

Referring to FIG. 5, s=6, t=5, the characteristic equation of the firstindex generator 310 is chosen to be f₁(x)=x⁶+x⁵+1 from a 6-degreeprimitive polynomial, and the initial value is chosen as “000001b”.Accordingly, C5=1, C4=C3=C2=C1=0, and C0=1, and initial values ofregisters R1, R2, R3, R4, R5 are all “0b” and R6 is “1b”.

When “s” is set as “6”, the first index generator 310, as shown in FIG.5 comprises six registers R1, R2 . . . R6 connected in series with eachcoupled to receive a corresponding initial value 501, 502 . . . 506; andfive adders 510, 520, 530, 540 and 550 each connected between every tworegisters to add an output value from the corresponding registers R1, R2. . . R6, which are known as a row index.

At the first clock, since values 511 to 515 are output from theregisters R1 through R5, as a row index, the row index 511 through 515corresponds to the initial values 501 to 505. Thus, the row index 511through 515 at the first clock is comprised of 0, 0, 0, 0, 1, which iscalled a row index vector “00001 b”.

At the second clock, a value of the register R2 corresponds to the valueof the register R1 at the first clock; a value of the register R3corresponds to the value of the register R2 at the first clock; a valueof the register R4 corresponds to the value of the register R3 at thefirst clock; and a value of the register R5 corresponds to the value ofthe register R4 at the first clock. A value of the register R6 at thesecond clock is determined by adding the value of the register R6 withthe value of the register R5 at the first clock, since the previousvalue of the register R6 is fed back to an adder 550 through a feedbackline 521 to be added with the (previous) value of the register R5. Avalue of the register R1 at the second clock is determined to be thevalue of the register R6 at the first clock, since the value is fed backto the register R1 through a feedback line 521.

As a result, values of the registers R1 through R5 are each 1, 0, 0, 0,0 at the second clock, resulting in the row vector “10000b”, which is“1” in decimal (by the definition that the value of the register R1 isthe least significant bit).

Row indexes at the third to n-th clocks are generated in the same way asdescribed above.

FIG. 6 illustrates a table of information 600 regarding the first indexgenerator shown in FIG. 5.

Referring to FIG. 5, as described above, the characteristic equation ischosen to be f₁(x)=x⁶+x⁵+1 from a 6-degree primitive polynomial, and theinitial value is chosen as “000001 b”. The number of row indexes outputby the first index generator 310 is 2^(s)−1=2⁶−1=63, among which thenumber 0 is output 2^(s−t)−1=2⁶⁻⁵−1=1 time and the other numbers 1 to 31are each output 2^(s−t)=2⁶⁻⁵=2 times.

FIG. 7 is a block diagram of the second index generator 320, shown inFIG. 3, according to an embodiment of the present invention.

In the second index generator 320, a feedback line is different fromthat of the first index generator 310, shown in FIG. 5, but operationsare the same. For example, like the first index generator 310, as shownin FIG. 5, the second index generator 320 also comprises six registersR1, R2 . . . R6 connected in series with each coupled to receive acorresponding initial value 701, 702 . . . 706; and five adders 710,720, 730, 740 and 750 each connected between every two registers to addan output value from the corresponding registers R1, R2 . . . R6, whichare known as a row index.

The characteristic equation of the second index generator 320 can bearbitrarily chosen from a primitive polynomial that satisfies Equations(3) and (4), regardless of the characteristic equation of the firstindex generator 310. However, an initial value 701 through 706 of thesecond index generator 320 should be chosen such that row index vectors511 through 515 output by the first index generator 310, and row indexvectors 711 through 715 output by the second index generator 600, arenot the same at the same clock.

Similarly, initial values of the third, fourth, . . . , Wc-th indexgenerators are chosen such that row indexes output by corresponding rowindex generators are not the same at the same clock.

The initial values can be determined empirically through simulation.Since the row weight Wc is a very small number, for typical LDPC codes,performing a simulation to determine initial values satisfying the aboveconditions is not difficult.

FIG. 8 illustrates a table of information 800 regarding the second indexgenerator shown in FIG. 7.

Referring to FIG. 8, the characteristic equation is chosen to bef₁(x)=x⁶+x⁵+x⁴+x+1 from a 6-degree primitive polynomial, and the initialvalue of the second index generator 320 is chosen to be “001111 b”, bywhich none of 63 row indexes output by the second index generator 320are the same as the row index output by the first index generator 310 atthe same clock, as shown in FIG. 6. Likewise, the initial value of eachindex generator 310, 320 or 330 should be chosen such that index vectorsoutput from all the index generators are different from each other atthe same clock.

The memory space (in bits) required when storing the parity check matrixin memory as previously known in the art will now be compared between inthe case of storing the parity check matrix in a memory and in the caseof constructing the parity check matrix using the apparatus according toexample embodiments of the present invention. Here, a parity checkmatrix having m=2⁹=512, n=2⁹×17=512×17=8704, and Wc=3 is taken as anexample.

In the case of storing the parity check matrix in a memory, 9 bits areneeded to store a row index of a “1”, and thus 9×3×8704=235008 bits areneeded to store the parity check matrix.

Meanwhile, according to the present invention, “t” and the minimum “s”(s_min) that satisfy Equation (2) for m=512 and n=8704, are 9 and 14,respectively, which means that an index generator requires 14 bits.Therefore, compared to the case of storing the parity check matrix, amuch smaller number of only 14×Wc=14×3=42 bits is all the memory spacerequired for constructing a parity check matrix.

In addition, if the characteristic equation of a modular shift registergenerator (MSRG) as shown in FIG. 4 is chosen to be a primitiveequation, the number of Wr of a resulting parity check matrix is moreregular, which makes decoding easier.

FIG. 9 is a flowchart of methods of constructing a parity check matrixaccording to an embodiment of the present invention.

In operation 910, s-bit initial value is input and stored bit-by-bit ins registers of a modular shift register generator (MSRG).

In operation 920, of all the bits stored in the s registers, a bit inthe last register, a least significant bit (LSB), is fed-back to beselectively provided to adders connected between the registers. Whetherthe LSB is fed back is determined by coefficients of a characteristicequation of the modular shift register generator (MSRG), thecharacteristic equation which is preferably a primitive polynomial.

In operation 930, in each adder, a bit value stored in a correspondingregister before the adder is added with the fed-back value.

In operation 940, all the bits resulting from the addition are stored incorresponding registers next to the adders.

In operation 950, values of t out of s registers are output as a rowindex of a “1”.

Operations 920 through 940 are performed during one clock cycle.Therefore, at every clock, every row index of a “1” is output.

As described in the foregoing, the present invention advantageouslyprovides methods and apparatus for constructing a parity check matrix byusing shift registers, which can significantly reduce large amounts ofmemory required for encoding and decoding purposes. Such methods andapparatus for constructing a parity check matrix according to exampleembodiments of the present invention can also be implemented as acomputer program. Codes and code segments constituting the computerprogram may readily be inferred by those skilled in the art. Thecomputer programs may be recorded on computer-readable media and readand executed by computers. Such computer-readable media include allkinds of storage devices, such as ROM, RAM, CD-ROM, magnetic tape,floppy discs, optical data storage devices, etc. The computer readablemedia also include everything that is realized in the form of carrierwaves, e.g., transmission over the Internet. The computer-readable mediamay be distributed to computer systems connected to a network, and codeson the distributed computer-readable media may be stored and executed ina decentralized fashion.

While there have been illustrated and described what are considered tobe example embodiments of the present invention, it will be understoodby those skilled in the art and as technology develops that variouschanges and modification may be made, and equivalents may be substitutedfor elements thereof without departing from the spirit and scope of thepresent invention. Many modifications may be made to adapt the teachingsof the present invention to a particular situation without departingfrom the scope thereof. Accordingly, it is intended, therefore, that thepresent invention not be limited to the various example embodimentsdisclosed, but that the present invention includes all embodimentsfalling within the scope of the appended claims.

1. An apparatus for constructing a low density parity check matrix,comprising: at least one index generator for generating row indexes of“1”s, which indicate row positions of the “1”s in each column of theparity check matrix, wherein the index generator is implemented by amodular shift register generator that generates a row index of a “1” ateach clock.
 2. The apparatus as claimed in claim 1, wherein the indexgenerator comprises: “s” number of registers connected in series toreceive an initial value of “s” bits, store the initial valuebit-by-bit, and each shift corresponding stored bit to a succeedingregister at a clock; a feedback line through which a bit value stored ina last one of the registers is selectively fed-back; and an adderconnected between every two registers, to add a bit value of a precedingregister with a fed-back value and provide a resulting value to thesucceeding register.
 3. The apparatus as claimed in claim 1, wherein therow index is a vector of t bits output from t number of registersselected from among the s number registers, the s and t satisfying thefollowing equations:m=2^(t)n≦2^(s)−1, where m is the number of rows and n is the number of columnsof the parity check matrix.
 4. The apparatus as claimed in claim 2,wherein the feedback line includes a switch with a coefficient chosensuch that all the vectors output from the registers during 2^(s)−1clocks are different from each other.
 5. The apparatus as claimed inclaim 4, wherein the coefficient of the switch is chosen from amongcoefficients of a primitive polynomial p(x) into which x^(v)−1 can bedivided, where v is a smallest possible positive number satisfying thefollowing equation: v=p^(u)−1, and where the primitive polynomial is anirreducible polynomial of degree of u, having coefficients being any of0 through p−1, that is p(x) IN GF(p)[x], the p being any prime number.6. A method of constructing a low-density parity check matrix,comprising: generating at least one index of a “1”, which represents aposition of the “1” in each column of a parity check matrix, wherein thegeneration of at least one index is implemented by a modular shiftregister generator that generates a row index of the “1” at each clock.7. The method as claimed in claim 6, wherein the at least one index isgenerated by: receiving and storing in a register an initial value of sbits; selectively feeding back a least significant bit of the initialvalue; adding a fed-back bit value to each bit of the initial value; andstoring as an output vector each of t bits selected from among the sbits resulting from the addition, and outputting the t-bit output vectoras a row index of the “1”.
 8. The method as claimed in claim 6, whereinthe row index of the “1” is a vector of t bits output from t number ofregisters arbitrarily selected from among the s number of registers, thes and t satisfying the following equation:m=2^(t)n≦2^(s)−1 where m is the number of rows and n is the number of columnsof the parity check matrix.
 9. The method as claimed in claim 7, whereinthe selectively feeding back is determined by coefficients of acharacteristic polynomial of the modular shift register generator, thecoefficients being chosen such that all vectors output during 2^(s)−1clocks are different.
 10. The method as claimed in claim 9, wherein thecoefficients are chosen from coefficients of a primitive polynomial p(x)into which x^(v)−1 can be divided, where v is a smallest possiblepositive number satisfying the following equation: v=p^(u)−1, and wherethe primitive polynomial is a irreducible polynomial of degree u, havingcoefficients being any of 0 through p−1, that is p(x) IN GF(p)[x], the pbeing any prime number.
 11. An apparatus for constructing a parity checkmatrix, comprising: a modular shift register generator to generateindexes of “1”s indicating positions of “1”s in the parity check matrix.12. The apparatus as claimed in claim 11, wherein a feedback line of themodular shift register generator is specified by a primitive polynomial.13. The apparatus as claimed in claim 11, wherein an initial value ofthe modular shift register generator is chosen such that at each clocknone of generated row indexes in a column are the same.
 14. Acomputer-readable medium comprising instructions that, when executed bya computer system, act as a modular shift register generator (MSRG) togenerate at least one index of a “1”, which represents a position of the“1” in each column of a parity check matrix at each clock.
 15. Thecomputer-readable medium as claimed in claim 14, wherein the index isgenerated by: receiving and storing in a register an initial value of sbits; selectively feeding back a least significant bit of the initialvalue; adding a fed-back bit value to each bit of the initial value; andstoring as an output vector each of t bits selected from among the sbits resulting from the addition, and outputting the t-bit output vectoras a row index of the “1”.
 16. An apparatus for constructing alow-density parity check (LDPC) matrix of M rows and N columns ofmessage and parity information for use in a LDPC coding scheme,comprising: a first index generator coupled to receive a first initialvalue, for generating a row index of the first element “1” inpredetermined bits for each column, from 1^(st) to N columns of theparity check matrix, at a different clock; a second index generatorcoupled to receive a second initial value, for generating a row index ofthe second element “1” in predetermined bits for each column, from1^(st) to N columns of the parity check matrix, at the different clock;and a N-th index generator coupled to receive a N-th initial value, forgenerating a row index of the N-th element “1” in predetermined bits foreach column, from 1^(st) to N columns of the parity check matrix, at thedifferent clock.
 17. The apparatus as claimed in claim 16, wherein thefirst, second and Nth index generators, each is implemented by a modularshift register generator (MSRG) comprising: “s” number of registersarranged in series to receive an initial value of “s” bits, to store theinitial value bit-by-bit, and to shift a corresponding stored bit valueto a succeeding register at a clock; a feedback line through which a bitvalue stored in a last register arranged in series, is selectivelyfed-back; s−1 number of adders, each disposed between every tworegisters, to add the stored bit value of a preceding register with thebit value fed-back, via the feedback line, and to provide a result valueto a succeeding register; and s−1 number of switches, each disposed onthe feedback line to a respective adder, to control transmission of thebit value fed-back, via the feedback line, to the respective adder,wherein outputs of “t” number of registers selected from among “s”number of registers correspond to row indexes of the “1”s of the paritycheck matrix.
 18. The apparatus as claimed in claim 17, wherein each rowvector of t bits output from “t” number of registers selected from amongthe s number registers, the s and t satisfying the following equations:m=2^(t)n≦2^(s)−1, where M is the number of rows and N is the number of columnsof the parity check matrix.
 19. The apparatus as claimed in claim 17,wherein each switch disposed on the feedback line is provided with acoefficient chosen such that all the vectors output from the registersduring 2^(s)−1 clocks are different from each other.
 20. The apparatusas claimed in claim 19, wherein the coefficient of the correspondingswitch is chosen from among coefficients of a primitive polynomial p(x)into which x^(v)−1 can be divided, where v is a smallest possiblepositive number satisfying the following equation: v=p^(u)−1, and wherethe primitive polynomial is an irreducible polynomial of degree of u,having coefficients being any of 0 through p−1, that is p(x) INGF(p)[x], the p being any prime number.
 21. The apparatus as claimed inclaim 16, wherein the first index generator comprises: 1^(st) to 6^(th)registers arranged in series, each to receive an initial value, to storethe initial value bit-by-bit, and to shift a corresponding stored bitvalue to a succeeding register at a clock; a feedback line through whicha bit value stored in the 6^(th) register arranged in series, isselectively fed-back; and an adder disposed between the 5^(th) and6^(th) registers, to add the stored bit value of the 5^(th) registerwith the bit value fed-back, via the feedback line, and to provide aresult value to the 6^(th) register; wherein outputs of the 1^(st) to5^(th) registers correspond to row indexes of the “1”s of the paritycheck matrix.
 22. The apparatus as claimed in claim 16, wherein thefirst index generator comprises: 1^(st) to 6^(th) registers arranged inseries, each to receive an initial value, to store the initial valuebit-by-bit, and to shift a corresponding stored bit value to asucceeding register at a clock; a feedback line through which a bitvalue stored in the 6^(th) register arranged in series, is selectivelyfed-back; a first adder disposed between the 5^(th) and 6^(th)registers, to add the stored bit value of the 5^(th) register with thebit value fed-back, via the feedback line, and to provide a result valueto the 6^(th) register; a second adder disposed between the 4^(th) and5^(th) registers, to add the stored bit value of the 4^(th) registerwith the bit value fed-back, via the feedback line, and to provide aresult value to the 5^(th) register; and a third adder disposed betweenthe 1^(st) and 2^(nd) registers, to add the stored bit value of the1^(st) register with the bit value fed-back, via the feedback line, andto provide a result value to the 2^(nd) register; wherein outputs of the1^(st) to 5^(th) registers correspond to row indexes of the “1”s of theparity check matrix.
 23. A method for constructing a low-density paritycheck (LDPC) matrix of M rows and N columns of message and parityinformation for use in an LDPC coding scheme, comprising: obtaining amodular shift register generator (MSRG) comprising “s” number ofregisters connected in series, and “s−1” adders each disposed betweenevery two registers; storing, at the s” number of registers arranged inseries, an initial value of “s” bits, and shifting a correspondingstored bit value to a succeeding register at a clock; selectivelyfeeding back a bit value stored in a last register, via a feedback line;adding, at the s−1 number of adders each disposed between every tworegisters, the stored bit value of a preceding register with the bitvalue fed-back, via the feedback line, and producing a result value to asucceeding register; and outputting, from “t” number of registersselected from among “s” number of registers, row indexes of the “1”s ofthe parity check matrix.
 24. The method as claimed in claim 23, whereineach row vector of t bits output from “t” number of registers selectedfrom among the s number registers, the s and t satisfying the followingequations:m=2^(t)n≦2^(s)−1, where M is the number of rows and N is the number of columnsof the parity check matrix.
 25. The method as claimed in claim 24,wherein the feedback line is provided with a switch having a coefficientchosen such that all the vectors output from the registers during2^(s)−1 clocks are different from each other.
 26. The method as claimedin claim 25, wherein the coefficient of the corresponding switch ischosen from among coefficients of a primitive polynomial p(x) into whichx^(v)−1 can be divided, where v is a smallest possible positive numbersatisfying the following equation: v=p^(u)−1, and where the primitivepolynomial is an irreducible polynomial of degree of u, havingcoefficients being any of 0 through p−1, that is p(x) IN GF(p)[x], the pbeing any prime number.